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Ultra-Low Power, 1-Channel, Capacitance Converter for Proximity Sensing AD7151
FEATURES
Ultra-low power 2.7 V to 3.6 V, 70 A Response time: 10 ms Adaptive environmental compensation 1 capacitance input channel Sensor capacitance (CSENS) 0 pF up to 13 pF Sensitivity to 1 fF EMC tested 2 modes of operation Standalone with fixed settings Interfaced to a microcontroller for user-defined settings Proximity detection output flag 2-wire serial interface (I2C compatible) Operating temperature -40C to +85C 10-lead MSOP package
GENERAL DESCRIPTION
The AD7151 delivers a complete signal processing solution for capacitive proximity sensors, featuring an ultra-low power converter with fast response time. The AD7150 is a 2-channel alternative to the AD7151. The AD7151 uses Analog Devices, Inc., capacitance-to-digital converter (CDC) technology, which combines features important for interfacing to real sensors, such as high input sensitivity and high tolerance of both input parasitic ground capacitance and leakage current. The integrated adaptive threshold algorithm compensates for any variations in the sensor capacitance due to environmental factors like humidity and temperature or due to changes in the dielectric material over time. By default, the AD7151 operates in standalone mode using the fixed power-up settings and indicates detection on a digital output. Alternatively, the AD7151 can be interfaced to a microcontroller via the serial interface, the internal registers can be programmed with user-defined settings, and the data and status can be read from the part. The AD7151 operates with a 2.7 V to 3.6 V power supply. It is specified over the temperature range of -40C to +85C.
APPLICATIONS
Proximity sensing Contactless switching Position detection Level detection
FUNCTIONAL BLOCK DIAGRAM
VDD
AD7151
CIN CSENS - CDC DIGITAL FILTER SERIAL INTERFACE SCL SDA
EXC
EXCITATION
THRESHOLD
OUT
07086-001
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD7151 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Architecture and Main Features ................................................... 10 Capacitance-to-Digital Converter............................................ 10 CAPDAC ..................................................................................... 10 Comparator and Threshold Modes.......................................... 11 Adaptive Threshold.................................................................... 11 Data Average ............................................................................... 11 Sensitivity..................................................................................... 12 Hysteresis..................................................................................... 12 Timeout........................................................................................ 12 AutoCAPDAC Adjustment ....................................................... 13 Power-Down Timer ................................................................... 13 Power Supply Monitor ............................................................... 13 Register Descriptions ..................................................................... 14 Status Register ............................................................................. 15 Data Register ............................................................................... 16 Average Register ......................................................................... 16 Fixed Threshold Register........................................................... 16 Sensitivity Register ..................................................................... 16 Timeout Register ........................................................................ 17 Setup Register ............................................................................. 18 Configuration Register .............................................................. 19 Power-Down Timer Register .................................................... 20 CAPDAC Register...................................................................... 20 Serial Number Register.............................................................. 20 Chip ID Register......................................................................... 20 Serial Interface ................................................................................ 21 Read Operation........................................................................... 21 Write Operation.......................................................................... 21 AD7151 Reset ............................................................................. 22 General Call ................................................................................ 22 Hardware Design Considerations ................................................ 23 Overview ..................................................................................... 23 Parasitic Capacitance to Ground.............................................. 23 Parasitic Resistance to Ground................................................. 23 Parasitic Parallel Resistance ...................................................... 23 Parasitic Serial Resistance ......................................................... 24 Input Overvoltage Protection ................................................... 24 Input EMC Protection ............................................................... 24 Power Supply Decoupling and Filtering.................................. 24 Application Examples ................................................................ 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 26
REVISION HISTORY
11/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7151 SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = 0 V; -40C to +85C, single-ended capacitance mode, unless otherwise noted. Table 1.
Parameter CAPACITIVE INPUT Conversion Input Range CIN to EXC 2 Min 3.2 1.6 0.8 0.4 Typ 4 2 1 0.5 2.0 1.6 1.4 1.0 150 15 -20 0.5 -2 50 5 0.1 4 10 12.5 200 0.25 75 VDD/2 16 +2 200 +20 Max Unit 1 pF pF pF pF fF fF fF fF pF M k % % % fF fF % fF/V pF fF LSB % of CIN Range V kHz pF M V V V V A pF V A V ISINK = -6.0 mA VOUT = VDD ISINK = -4 mA ISOURCE = 4 mA Test Conditions/Comments 4 pF input range 2 pF input range 1 pF input range 0.5 pF input range 4 pF input range 2 pF input range 1 pF input range 0.5 pF input range
Resolution 3
Allowed Capacitance CIN to GND3 Allowed Resistance CIN to GND3 Allowed Serial Resistance3 Gain Error Gain Deviation over Temperature3 Gain Matching Between Ranges3 Offset Error3 Offset Deviation over Temperature3 Integral Nonlinearity (INL)3 Power Supply Rejection3 CAPDAC2 Full Range Resolution (LSB)3 Differential Nonlinearity (DNL)3 AutoDAC Increment/Decrement3 EXCITATION Voltage Frequency Allowed Capacitance EXC to GND3 Allowed Resistance EXC to GND3 LOGIC OUTPUT (OUT) Output Low Voltage (VOL) Output High Voltage (VOH) SERIAL INTERFACE INPUTS (SCL, SDA) Input High Voltage (VIH) Input Low Voltage (VIL) Input Leakage Current Input Pin Capacitance OPEN-DRAIN OUTPUT (SDA) Output Low Voltage (VOL) Output High Leakage Current (IOH) POWER SUPPLY MONITOR VDD Threshold Voltage
CIN and EXC pins disconnected CIN and EXC pins disconnected
25
15.4 1
16.3 300
0.4 VDD - 0.6 1.5 0.1 6 0.8 5
0.4 0.1 2.45 5 2.65
Rev. 0 | Page 3 of 28
AD7151
Parameter POWER REQUIREMENTS VDD-to-GND Voltage IDD Current 4 IDD Current Power-Down Mode4 Min 2.7 70 1 3 Typ Max 3.6 80 5 10 Unit 1 V A A A Test Conditions/Comments VDD = 3.3 V, nominal Temperature 25C Temperature = 85C
1 2
Capacitance units: one picofarad (1 pF) = 1 x 10-12 farad (F); one femtofarad (1 fF) = 10-15 farad (F). The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can, therefore, be up to the sum of the CAPDAC value and the conversion input range. With the autoCAPDAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC nominal input range. 3 Specification is not production tested but is supported by characterization data at initial product release. 4 Digital inputs equal to VDD or GND.
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; -40C to +85C, unless otherwise noted. Table 2.
Parameter CONVERTER Conversion Time Wake-Up Time from Power-Down Mode 1, 2 Power-Up Time1, 3 Reset Time1, 4 SERIAL INTERFACE 5, 6 SCL Frequency SCL High Pulse Width, tHIGH SCL Low Pulse Width, tLOW SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Hold Time (Start Condition), tHD;STA Setup Time (Start Condition), tSU;STA Data Setup Time, tSU;DAT Setup Time (Stop Condition), tSU;STO Data Hold Time (Master), tHD;DAT Bus-Free Time (Between Stop and Start Condition), tBUF
1 2
Min
Typ
Max 10
Unit ms ms ms ms
Test Conditions/Comments
0.3 2 2 0 0.6 1.3 400
See Figure 2. kHz s s s s s s s s ns s
0.3 0.3 0.6 0.6 0.1 0.6 10 1.3
After this period, the first clock is generated. Relevant for repeated start condition.
Specification is not production tested but is supported by characterization data at initial product release. Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion. 3 Power-up time is the maximum delay between the VDD crossing the minimum level (2.7 V) and either the start of conversion or when ready to receive a serial interface command. 4 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface command. 5 Sample tested during initial release to ensure compliance. 6 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF.
tLOW
SCL
tR
tF
tHD;STA
tHD;STA
SDA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
tBUF
P S
S
P
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 4 of 28
07086-002
AD7151 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter Positive Supply Voltage VDD to GND Voltage on Any Input or Output to GND ESD Rating HBM (ESD Association Human Body Model, S5.1) ESD Rating FICDM (Field-Inducted Charged Device Model) Operating Temperature Range Storage Temperature Range Maximum Junction Temperature MSOP Package JA, Thermal Impedance-to-Air JC, Thermal Impedance-to-Case Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating -0.3 V to +3.9 V -0.3 V to VDD + 0.3 V 4 kV 1 kV -40C to +85C -65C to +150C 150C 206C/W 44C/W 260(+0/-5)C 10 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 28
AD7151 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1 VDD 2 NC 3 CIN 4 NC 5
10 SDA
AD7151
TOP VIEW (Not to Scale)
9 8 7 6
SCL NC OUT
07086-003
EXC
NC = NO CONNECT
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic GND VDD NC CIN NC EXC OUT NC SCL SDA Description Ground Pin. Power Supply Voltage. This pin should be decoupled to GND using a low impedance capacitor, for example, 0.1 F X7R multilayer ceramic. This pin should be left as an open circuit or connected to GND. CDC Capacitive Input. The measured capacitance (sensor) is connected between the EXC pin and the CIN pin. This pin should be left as an open circuit. CDC Excitation Output. The measured capacitance is connected between the EXC pin and the CIN pin. Logic Output. High level on this output indicates proximity detected on the capacitive input. This pin should be left as an open circuit. Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if not provided elsewhere in the system. Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided elsewhere in the system.
Rev. 0 | Page 6 of 28
AD7151 TYPICAL PERFORMANCE CHARACTERISTICS
300 0.10
200
0.05
OFFSET ERROR (fF)
GAIN ERROR (%FS)
07086-104
100
0
0
-0.05
0
50
100
150
200
250
300
0
50
100
150
200
250
300
CAPACITANCE CIN TO GND (pF)
CAPACITANCE EXC TO GND (pF)
Figure 4. Capacitance Input Offset Error vs. Capacitance CIN to GND, VDD = 3.3 V, EXC Pin Open Circuit
2
Figure 7. Capacitance Input Gain Error vs. Capacitance EXC to GND, VDD = 3.3 V, CIN to EXC = 2 pF
200
0 100 -2
OFFSET ERROR (fF)
GAIN ERROR (%FS)
0
-4
-100 -6
07086-105
0
50
100
150
200
250
300
1
10
100
1000
CAPACITANCE CIN TO GND (pF)
RESISTANCE CIN TO GND (M)
Figure 5. Capacitance Input Gain Error vs. Capacitance CIN to GND, VDD = 3.3 V, CIN to EXC = 2 pF
2
Figure 8. Capacitance Input Offset Error vs. Resistance CIN to GND, VDD = 3.3 V, EXC Pin Open Circuit
10
1
5
GAIN ERROR (%FS)
OFFSET ERROR (fF)
0
0
-1
-5
07086-106
0
50
100
150
200
250
300
1
10
100
1000
CAPACITANCE EXC TO GND (pF)
RESISTANCE CIN TO GND (M)
Figure 6. Capacitance Input Offset Error vs. Capacitance EXC to GND, VDD = 3.3 V, CIN Pin Open Circuit
Figure 9. Capacitance Input Gain Error vs. Resistance CIN to GND, VDD = 3.3 V, CIN to EXC = 2 pF
Rev. 0 | Page 7 of 28
07086-109
-2
-10
07086-108
-8
-200
07086-107
-100
-0.10
AD7151
10 10
5
OFFSET ERROR (fF) GAIN ERROR (%FS)
5
0
0
-5
-5
0
2
4
6
8
10
1
10
100
1000
RESISTANCE EXC TO GND (M)
PARALLEL RESISTANCE (M)
Figure 10. Capacitance Input Offset Error vs. Resistance EXC to GND, VDD = 3.3 V, CIN Pin Open Circuit
0.50
Figure 13. Capacitance Input Gain Error vs. Parallel Resistance, VDD = 3.3 V, CIN to EXC = 2 pF
4
0.25
GAIN ERROR (%FS) OFFSET ERROR (fF)
2
0
0
-0.25
-2
-25
0
25
50
75
100
RESISTANCE EXC TO GND (M)
TEMPERATURE (C)
Figure 11. Capacitance Input Gain Error vs. Resistance EXC to GND, VDD = 3.3 V, CIN to EXC = 2 pF
2
Figure 14. Capacitance Input Offset Error vs. Temperature, VDD = 3.3 V, CIN and EXC Pins Open Circuit
0.2
1
GAIN ERROR (%FS) GAIN ERROR (%FS)
0.1
0
0
-0.1
-1 -0.2
-25
0
25
50
75
100
SERIAL RESISTANCE (k)
TEMPERATURE (C)
Figure 12. Capacitance Input Gain Error vs. Serial Resistance VDD = 3.3 V, CIN to EXC = 2 pF
Figure 15. Capacitance Input Gain Error vs. Temperature, VDD = 3.3 V, CIN to EXC = 2 pF
Rev. 0 | Page 8 of 28
07086-115
0
50
100
150
200
250
07086-112
-2
-0.2 -50
07086-114
0
2
4
6
8
10
07086-111
-0.50
-4 -50
07086-113
07086-110
-10
-10
AD7151
2 0
EXC FREQUENCY ERROR (%)
1
-20
0
GAIN (dB)
07086-116
-40
-1
-60
-25
0
25
50
75
100
0
0.5
1.0
1.5
2.0
2.5
TEMPERATURE (C)
INPUT SIGNAL FREQUENCY (kHz)
Figure 16. EXC Frequency Error vs. Temperature, VDD = 3.3 V
2
Figure 18. Capacitance to Digital Converter Frequency Response
0.50
EXC FREQUENCY ERROR (%)
1
0.25
0
CAPDAC DNL (LSB)
0
-1
-0.25
3.0 VDD (V)
3.3
3.6
07086-117
0
16
32 CAPDAC CODE
48
64
Figure 17. EXC Frequency Error vs. VDD
Figure 19. CAPDAC Differential Nonlinearity (DNL), VDD = 3.3 V
Rev. 0 | Page 9 of 28
07086-119
-2 2.7
-0.50
07086-118
-2 -50
-80
AD7151 ARCHITECTURE AND MAIN FEATURES
3.3V VDD
CLOCK GENERATOR
POWER-DOWN TIMER
POWER SUPPLY MONITOR SCL
CIN
- CDC
DIGITAL FILTER
SERIAL INTERFACE
SDA
PROGRAMMING INTERFACE
CX
CAPDAC
THRESHOLD
OUT
DIGITAL OUTPUT
EXC
EXCITATION
AD7151
GND
07086-010
Figure 20. AD7151 Block Diagram
The AD7151 core is a high performance capacitance-to-digital converter (CDC) that allows the part to be interfaced directly to a capacitive sensor. The comparator compares the CDC result with thresholds, either fixed or dynamically adjusted by the on-chip adaptive threshold algorithm engine. Thus, the output indicates a defined change in the input sensor capacitance. The AD7151 also integrates an excitation source and CAPDAC for the capacitive inputs, an input multiplexer, a complete clock generator, a power-down timer, a power supply monitor, control logic, and an I2C(R)-compatible serial interface for configuring the part and accessing the internal CDC data and status, if required in the system (see Figure 20).
CAPACITANCE TO DIGITAL CONVERTER (CDC) CLOCK GENERATOR 0x000 TO 0xFFF DATA DIGITAL FILTER
CIN CX 0pF TO 4pF EXC
- MODULATOR
EXCITATION
07086-011
Figure 21. CDC Simplified Block Diagram
CAPDAC
The AD7151 CDC core maximum full-scale input range is 4 pF. However, the part can accept a higher capacitance on the input, and the offset (nonchanging component) capacitance of up to 10 pF can be balanced by a programmable on-chip CAPDAC.
CAPDAC 10pF CIN CSENS 10pF TO 14pF EXC
CAPACITANCE-TO-DIGITAL CONVERTER
Figure 21 shows the CDC simplified functional diagram. The converter consists of a second-order sigma delta (-), charge balancing modulator and a third-order digital filter. The measured capacitance CX is connected between an excitation source and the - modulator input. The excitation signal is applied on the CX during the conversion, and the modulator continuously samples the charge going through the CX. The digital filter processes the modulator output, which is a stream of 0s and 1s containing the information in 0 and 1 density. The data is processed by the adaptive threshold engine and output comparators; the data can be also read through the serial interface. The AD7151 is designed for floating capacitive sensors. Therefore, both CX plates have to be isolated from ground or any other fixed potential node in the system. The AD7151 features slew rate limiting on the excitation voltage output, which decreases the energy of higher harmonics on the excitation signal and dramatically improves the system electromagnetic compatibility (EMC).
0x000 TO 0xFFF DATA 0pF TO 4pF CDC
Figure 22. Using CAPDAC
The CAPDAC can be understood as a negative capacitance connected internally to the CIN pin. The CAPDAC has a 6-bit resolution and a monotonic transfer function. Figure 22 shows how to use the CAPDAC to shift the CDC 4 pF input range to measure capacitance between 10 pF and 14 pF.
Rev. 0 | Page 10 of 28
07086-012
AD7151
COMPARATOR AND THRESHOLD MODES
The AD7151 comparator and its threshold can be programmed to operate in several different modes. In an adaptive mode, the threshold is dynamically adjusted and the comparator output indicates fast changes and ignores slow changes in the input (sensor) capacitance. Alternatively, the threshold can be programmed as a constant (fixed) value, and the output then indicates any change in the input capacitance that crosses the defined fixed threshold. The AD7151 logic output (active high) indicates either a positive or a negative change in the input capacitance, in both adaptive and fixed threshold modes (see Figure 23 and Figure 24).
POSITIVE CHANGE POSITIVE THRESHOLD INPUT CAPACITANCE OUTPUT ACTIVE
INPUT OUTSIDE THRESHOLD WINDOW POSITIVE THRESHOLD INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT ACTIVE
07086-016
07086-018
OUTPUT TIME
Figure 26. Out-Window (Adaptive) Threshold Mode
ADAPTIVE THRESHOLD
In an adaptive mode, the thresholds are dynamically adjusted, ensuring indication of fast changes (for example an object moving close to a capacitive proximity sensor) and eliminating slow changes in the input (sensor) capacitance, usually caused by environment changes such as humidity or temperature or changes in the sensor dielectric material over time (see Figure 27).
FAST CHANGE SLOW CHANGE INPUT CAPACITANCE THRESHOLD
TIME
Figure 23. Positive Threshold Mode Indicates Positive Change in Input Capacitance
OUTPUT
NEGATIVE CHANGE INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT ACTIVE
07086-013
OUTPUT
OUTPUT ACTIVE
07086-017
TIME
Figure 27. Adaptive Threshold Indicates Fast Changes and Eliminates Slow Changes in Input Capacitance
DATA AVERAGE
The adaptive threshold algorithm is based on an average calculated from previous CDC output data. The response of the average to an input capacitance step change (more exactly, response to the change in the CDC output data) is an exponential settling curve, which can be characterized by the following equation:
07086-014
OUTPUT TIME
Figure 24. Negative Threshold Mode Indicates Negative Change in Input Capacitance
Additionally, for the adaptive mode only, the comparator can work as window comparator, indicating input either inside or outside a selected sensitivity band (see Figure 25 and Figure 26).
POSITIVE THRESHOLD INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT ACTIVE
07086-015
Average ( N ) = Average (0) + Change (1 - e N / TimeConst )
where: Average(N) is the value of average N complete CDC conversion cycles after a step change on the input. Average(0) is the value before the step change. TimeConst can be selected in the range between 2 and 65,536, in steps of power of 2, by programming the ThrSettling bits in the setup register. See Figure 28 and the Register Descriptions section.
INPUT CAPACITANCE (CDC DATA) CHANGE
INPUT INSIDE THRESHOLD WINDOW
OUTPUT TIME
Figure 25. In-Window (Adaptive) Threshold Mode
DATA AVERAGE RESPONSE TIME
Figure 28. Data Average Response to Data Step Change
Rev. 0 | Page 11 of 28
AD7151
SENSITIVITY
In adaptive threshold mode, the output comparator threshold is set as a defined distance (sensitivity) above the data average, below the data average, or both, depending on the selected threshold mode of operation (see Figure 29). The sensitivity value is programmable in the range 0 to 255 LSBs of the 12-bit CDC converter (see the Register Descriptions section).
DATA POSITIVE THRESHOLD SENSITIVITY DATA AVERAGE SENSITIVITY NEGATIVE THRESHOLD OUTPUT ACTIVE
07086-019
The timeout can be set independently for approaching (for change in data toward the threshold) and for receding (for change in data away from the threshold). See Figure 32, Figure 33, and the Register Descriptions section.
DATA AVERAGE + SENSITIVITY DATA AVERAGE DATA AVERAGE - SENSITIVITY LARGE CHANGE IN DATA
TIMEOUT
TIME
Figure 31. Threshold Timeout After a Large Change in CDC Data
TIMEOUT APPROACHING INPUT CAPACITANCE THRESHOLD DATA AVERAGE
TIME
Figure 29. Threshold Sensitivity
HYSTERESIS
In adaptive threshold mode, the comparator features hysteresis. The hysteresis is fixed to one-fourth of the threshold sensitivity and can be programmed on or off. The comparator does not have hysteresis in the fixed threshold mode.
DATA POSITIVE THRESHOLD
OUTPUT ACTIVE
TIME
Figure 32. Approaching Timeout in Negative Threshold Mode Shortens False Output Trigger
HYSTERSIS
TIMEOUT RECEDING
DATA AVERAGE OUTPUT ACTIVE
07086-020
LARGE CHANGE
OUTPUT
TIME
INPUT CAPACITANCE THRESHOLD OUTPUT ACTIVE OUTPUT TIME
Figure 30. Threshold Hysteresis
TIMEOUT
In the case of a large, long change in the capacitive input, when the data average adapting to a new condition may take too long, a timeout can be set. The timeout becomes active (counting) when the CDC data goes outside the band of data average sensitivity. When the timeout elapses (a defined number of CDC conversions is counted), the data average (and thus the threshold) is forced to follow the new CDC data value immediately (see Figure 31).
Figure 33. Positive Timeout in Negative Threshold Mode Shortens Period of Missing Output Trigger
Rev. 0 | Page 12 of 28
07086-023
07086-022
OUTPUT
07086-021
AD7151
AUTOCAPDAC ADJUSTMENT
In adaptive threshold mode, the part can dynamically adjust the CAPDAC to keep the CDC in an optimal operating capacitive range. When the AutoDAC function is enabled, the CAPDAC value is automatically incremented when the data average exceeds three-fourths of the CDC full range, and the CAPDAC value is decremented when the data average goes below onefourth of the CDC full range. The AutoDAC increment or decrement step depends on the selected CDC capacitive input range. See the Setup Register section.
POWER SUPPLY MONITOR
When the AD7151 VDD power supply voltage drops below a defined level needed for correct CDC operation, the on-chip power supply monitor stops the adaptive threshold logic and holds it in reset. After the VDD reaches the required level, the threshold logic is released, and the data average is reset to the value of the first conversion finished at the correct power supply voltage. This feature prevents the adaptive threshold from being set incorrectly after a very slow rise of the VDD voltage or from being corrupted by accidental drops in the VDD voltage. The other AD7151 functions continue working below the power supply monitor threshold, down to approximately 1.0V..1.8V, the exact level depending on the manufacturing process variation. In the region of the low VDD voltage, the part is still accessible via the serial interface and continues conversion. However, the conversion results may be incorrect and, therefore, the data should not be considered valid if the part operates below the power supply monitor threshold. The status of the power supply monitor can be determined by reading the PwrDown bit in the AD7151 status register.
POWER-DOWN TIMER
In power sensitive applications, the AD7151 can be set to automatically enter power-down mode after a programmed period of time in which the output has not been activated. The AD7151 can be then returned to a normal operational mode either via the serial interface or by the power supply off/on sequence.
Rev. 0 | Page 13 of 28
AD7151 REGISTER DESCRIPTIONS
Table 5. Register Summary
Register Status Data High Data Low - - Average High Average Low - - Sensitivity Threshold High Timeout Threshold Low Setup - - - Configuration Power-Down Timer CAPDAC - Serial Number 3 Serial Number 2 Serial Number 1 Serial Number 0 Chip ID Pointer (Dec) (Hex) R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 R R R R R R R R R Bit 7 PwrDown 0 Bit 6 - 1 Bit 5 - 0 Bit 4 Bit 3 Default Value OUT DacStep 1 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Sensitivity (in adaptive threshold mode)/Threshold High Byte (in fixed threshold mode) 0x08 Timeout (in adaptive threshold mode)/Threshold Low Byte (in fixed threshold mode) 0x86 RngH RngL - ThrSettling (4-bit value) Hyst 0 0 0 0 0x00 0x00 0x00 ThrFixed 0 - 0 DacEn 1 ThrMD1 0 - 0 DacAuto 1 ThrMD0 0 EnConv - MD2 MD1 1 0 0 0 Power-Down Timeout (6-bit value) 0x00 DacValue (6-bit value) 0x00 0x00 Serial Number - Byte 3 (MSB) Serial Number - Byte 2 Serial Number - Byte 1 Serial Number - Byte 0 (LSB) Chip Identification Code MD0 1 0x0B 0 Bit 2 - 0 Bit 1 - 1 Bit 0 RDY 1
0x09 R/W 0x0A R/W 0x0B R/W 0x0C R/W 0x0D R/W 0x0E R/W 0x0F R/W 0x10 R/W 0x11 R/W 0x12 R/W 0x13 0x14 0x15 0x16 0x17 R R R R R
Rev. 0 | Page 14 of 28
AD7151
STATUS REGISTER
Address Pointer 0x00 8 Bits, Read-Only, Default Value 0x53 Before Conversion, 0x52 After Conversion
The status register indicates the status of the part. The register can be read via the 2-wire serial interface to query the status of the outputs, check the CDC finished conversion, and check whether the CAPDAC has been changed by the autoCAPDAC function. Table 6. Status Register Bit Map
Bit Mnemonic Default Bit 7 PwrDown 0 Bit 6 - 1 Bit 5 - 0 Bit 4 DacStep 1 Bit 3 OUT 0 Bit 2 - 0 Bit 1 - 1 Bit 0 RDY 1
Table 7. Status Register Bit Descriptions
Bit 7 6 5 4 3 2 1 0 Mnemonic PwrDown - - DacStep OUT - - RDY Description PwrDown = 1 indicates that the part is in a power-down mode or that the part VDD is below the power supply monitor threshold voltage. Bit not used, always reads 1. Bit not used, always reads 0. DacStep = 0 indicates that the CAPDAC value was changed during the last conversion as part of the AutoDac function. The bit value is updated after each finished CDC conversion. OUT = 1 indicates that the data (CIN capacitance) crossed the threshold, according to the selected comparator mode of operation. The bit value is updated after each finished CDC conversion. Bit not used, always reads 0. Bit not used, always reads 1. RDY = 0 indicates a finished CDC conversion. The bit is reset back to 1 when the data register is read via the serial interface or after the part reset or power-up.
Rev. 0 | Page 15 of 28
AD7151
DATA REGISTER
Address Pointer 0x01, 0x02 16 Bits, Read-Only, Default Value 0x0000
Data from the last complete capacitance-to-digital conversion reflects the capacitance on the input. Only the 12 MSBs (most significant bits) of the data register are used for the CDC result. The 4 LSBs (least significant bits) are always 0, as shown in Figure 34.
MSB DATA HIGH DATA LOW LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 12-BIT CDC RESULT 0
07086-044
AVERAGE REGISTER
Address Pointer 0x05, 0x06 16 Bits, Read-Only, Default Value 0x0000
This register shows the average calculated from the previous CDC data. The 12-bit CDC result corresponds to the 12 MSBs of the average register. The settling time of the average can be set by programming the ThrSettling bits in the setup register. The average register is overwritten directly with the CDC output data, that is, the history is forgotten if the timeout is enabled and elapses.
Figure 34. CDC Data Register
FIXED THRESHOLD REGISTER
Address Pointer 0x09, 0x0A 16 Bits, Read/Write, Factory Preset 0x0886
A constant threshold for the output comparator in the fixed threshold mode can be set using this register. The 12-bit CDC result corresponds to the 12 MSBs of the threshold register. The fixed threshold register shares the address pointer and location on-chip with the sensitivity and timeout registers. The fixed threshold register is not accessible in the adaptive threshold mode.
The nominal AD7151 CDC transfer function (an ideal transfer function excluding offset and/or gain error) maps the input capacitance between zero scale and full scale to output data codes between 0x3000 and 0xCFF0 only (see Table 8). Table 8. AD7151 Capacitance-to-Data Mapping
Data 0x0000 0x3000 0x8000 0xCFF0 0xFFF0 Input Capacitance Not valid, underrange Zero-scale (0 pF) Mid-scale (+1 pF) Full-scale (+2 pF) Not valid, overrange
SENSITIVITY REGISTER
Address Pointer 0x09 8 Bits, Read/Write, Factory Preset 0x08
The sensitivity register sets the distance of the positive threshold above the data average, and the distance of the negative threshold below the data average, in the adaptive threshold mode.
DATA POSITIVE THRESHOLD SENSITIVITY DATA AVERAGE SENSITIVITY NEGATIVE THRESHOLD OUTPUT ACTIVE
07086-024
The input capacitance can be calculated from the output data using the following equation:
C (pF) = Data - 12288 x Input _ Range 40944
where Input_Range = 4 pF, 2 pF, 1 pF, or 0.5 pF. The following is the same equation written with hexadecimal numbers:
C (pF) = Data - 0x3000 x Input _ Range 0x9FF 0
The data register is updated after a finished conversion, with one exception: when the serial interface read operation from the data register is in progress, the data register is not updated and the new capacitance conversion result is lost. The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent incorrect data reading through the serial interface, the two bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface.
TIME
Figure 35. Threshold Sensitivity
The sensitivity is an 8-bit value and is mapped to the lower eight bits of the 12-bit CDC data, that is, it corresponds to the 16-bit data register as shown in Figure 36.
SENSITIVITY BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DATA HIGH DATA LOW
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 12-BIT CDC RESULT
07086-025
Figure 36. Relation Between Sensitivity Register and CDC Data Register
Rev. 0 | Page 16 of 28
AD7151
TIMEOUT REGISTER
Address Pointer 0x0A 8 Bits, Read/Write, Factory Preset 0x86
Table 9. Timeout Register Bit Map
Bit Mnemonic Default Bits [7:4] TimeOutApr 0x08 Bits [3:0] TimeOutRec 0x06
When either the approaching or receding timeout elapses (that is, after the defined number of CDC conversions is counted), the data average (and thus the thresholds) is forced to follow the new CDC data value immediately. When the timeout register equals 0, timeouts are disabled.
DATA AVERAGE + SENSITIVITY DATA AVERAGE THRESHOLD LARGE CHANGE IN DATA TOWARDS THRESHOLD
The register sets timeouts for the adaptive threshold mode. The approaching timeout starts when the CDC data crosses the data average sensitivity band toward the threshold, according to the selected positive, negative, or window threshold mode. The approaching timeout elapses after the number of conversion cycles equals 2TimeOutApr, where TimeOutApr is the value of the four most significant bits of the timeout register. The receding timeout starts when the CDC data crosses the data average sensitivity band away from the threshold, according to the selected positive or negative threshold mode. The receding timeout is not used in the window threshold mode. The receding timeout elapses after the number of conversion cycles equals 2TimeOutRec, where TimeOutRec is the value of the four least significant bits of the timeout register.
TIMEOUT APPROACHING
TIME
Figure 37. Threshold Timeout Approaching After a Large Change in CDC Data Toward Threshold
TIMEOUT RECEDING
DATA AVERAGE + SENSITIVITY DATA AVERAGE LARGE CHANGE IN DATA AWAY FROM THE THRESHOLD
07086-027
THRESHOLD
TIME
Figure 38. Threshold Timeout Receding After a Large Change in CDC Data Away from Threshold
Rev. 0 | Page 17 of 28
07086-026
AD7151
SETUP REGISTER
Address Pointer 0x0B 8 Bits, Read/Write, Factory Preset 0x0B
Table 10. Setup Register Bit Map
Bit Mnemonic Default Bit 7 RngH 0 Bit 6 RngL 0 Bit 5 - 0 Bit 4 Hyst 0 Bit 3 Bit 2 Bit 1 ThrSettling (4-Bit Value) 0x0B Bit 0
Table 11. Setup Register Bit Descriptions
Bit 7 6 Mnemonic RngH RngL Description Range bits set the CDC input range and determine the step for the AutoDAC function. RngH 0 0 1 1 5 4 3 2 1 0 - Hyst ThrSettling RngL 0 1 0 1 Capacitive Input Range (pF) 2 0.5 1 4 AutoDAC Step (CAPDAC LSB) 4 1 2 8
This bit should be 0 for the specified operation. Hyst = 1 disables hysteresis in adaptive threshold mode. This bit has no effect in fixed threshold mode; hysteresis is always disabled in the fixed threshold mode. Determines the settling time constant of the data average and thus the settling time of the adaptive thresholds. The response of the average to an input capacitance step change (that is, response to the change in the CDC output data) is an exponential settling curve characterized by the following equation:
Average ( N ) = Average ( 0) + Change (1 - e N / TimeConst )
where: Average(N) is the value of average N complete CDC conversion cycles after a step change on the input Average(0) is the value before the step change TimeConst can be selected in the range between 2 and 65,536 conversion cycle multiples, in steps of power of 2, by programming the ThrSettling bits.
TimeConst = 2 (ThrSettlin g + 1)
See Figure 39.
INPUT CAPACITANCE (CDC DATA) CHANGE
TIME
Figure 39. Data Average Response to Data Step Change
Rev. 0 | Page 18 of 28
07086-028
DATA AVERAGE RESPONSE
AD7151
CONFIGURATION REGISTER
Address Pointer 0x0F 8 Bits, Read/Write, Factory Preset 0x19
Table 12. Configuration Register Bit Map
Bit Mnemonic Default Bit 7 ThrFixed 0 Bit 6 ThrMD1 0 Bit 5 ThrMD0 0 Bit 4 EnConv 1 Bit 3 - 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 1
Table 13.Configuration Register Bit Descriptions
Bit 7 Mnemonic ThrFixed Description ThrFixed = 1 sets the fixed threshold mode. The output reflects comparison of data and a fixed (constant) value of the threshold register. ThrFixed = 0 sets the adaptive threshold mode. The output reflects comparison of data to the adaptive threshold. The adaptive threshold is set dynamically, based on the history of the previous data. These bits set the output comparator mode. Output Active When ThrMD1 ThrMD0 Threshold Mode Adaptive Threshold Mode Fixed Threshold Mode 0 0 Negative data < average - sensitivity Data < Threshold 0 1 Positive data > average + sensitivity Data > Threshold 1 0 In-Window data > average - sensitivity AND data < average + sensitivity 1 1 Out-Window data < average - sensitivity OR data > average + sensitivity Enables conversion. This bit must be 1 for proper operation. This bit must be 0 for proper operation. Converter mode of operation setup. MD2 MD1 MD0 Mode Description 0 0 0 Idle Part is fully powered up but performing no conversion. 0 0 1 Continuous Part is repeatedly performing conversions, provided the Conversion EnConv bit is set. 0 1 0 Single Conversion Part performs a single conversion, provided the EnConv bit is set. After finishing the conversion(s), the part goes to the idle mode. 0 1 1 Power-Down Powers down the on-chip circuits, except the digital interface. 1 X X Reserved Do not use these modes.
6 5
ThrMD1 ThrMD0
4 3 2 1 0
EnConv - MD2 MD1 MD0
Rev. 0 | Page 19 of 28
AD7151
POWER-DOWN TIMER REGISTER
Address Pointer 0x10 8 Bits, Read/Write, Factory Preset 0x00
Table 14. Power-Down Timer Register Bit Map
Bit Mnemonic Default Bit 7 - 0 Bit 6 - 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Power-Down Timeout (6-Bit Value) 0x00 Bit 0
Table 15. Power-Down Timer Register Bit Descriptions
Bit [7:6] [5:0] Mnemonic Power-Down Timeout Description These bits must be 0 for proper operation Defines the period duration of the power-down timeout. If the output comparator output has not been activated during the programmed period, the part enters powerdown mode automatically. The part can be then returned to a normal operational mode either via the serial interface or by the power supply off/on sequence. The period is programmable in steps of four hours. For example, setting the value to 0x06 sets the duration to 24 hours. The maximum value of 0x3F corresponds to approximately 10.5 days. The value of 0x00 disables the power-down timeout, and the part does not enter power-down mode automatically.
CAPDAC REGISTER
Address Pointer 0x11 8 Bits, Read/Write, Factory Preset 0x00
Table 16. CAPDAC Register Bit Map
Bit Mnemonic Default Bit 7 DacEn 1 Bit 6 DacAuto 1 Bit 5 Bit 4 Bit 3 Bit 2 DacValue (6-Bit Value) 0x00 Bit 1 Bit 0
Table 17. CAPDAC Register Bit Descriptions
Bit 7 6 Mnemonic DacEn DacAuto Description DacEn = 1 enables capacitive DAC. DacAuto = 1 enables the AutoDAC function in the adaptive threshold mode. When the AutoDAC function is enabled, the part dynamically adjusts the CAPDAC to keep the CDC in an optimal operating capacitive range. The CAPDAC value is automatically incremented when the data average exceeds 3/4 of the CDC full range, and the CAPDAC value is decremented when the data average goes below 1/4 of the CDC full range. The AutoDAC increment or decrement step depends on the selected CDC capacitive input range. Bit has no effect in fixed threshold mode; the AutoDAC function is always disabled in the fixed threshold mode. CAPDAC value, Code 0x00 0 pF, Code 0x3F CAPDAC full range.
[5:0]
DacValue
SERIAL NUMBER REGISTER
Address Pointer 0x13, 0x14, 0x15, 0x16 32 Bits, Read Only, 0xXXXX
This register holds a serial number, unique for each individual part.
CHIP ID REGISTER
Address Pointer 0x17 8 Bits, Read Only, 0xXX
This register holds the chip identification code, used in factory manufacturing and testing.
Rev. 0 | Page 20 of 28
AD7151 SERIAL INTERFACE
The AD7151 supports an I2C-compatible 2-wire serial interface. The two wires on the serial bus (interface) are called SCL (clock) and SDA (data). These two wires carry all addressing, control, and data information one bit at a time over the bus to all connected peripheral devices. The SDA wire carries the data, while the SCL wire synchronizes the sender and receiver during the data transfer. The devices on the bus are classified as either master or slave devices. A device that initiates a data transfer message is called a master, while a device that responds to this message is called a slave. To control the AD7151 device on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-tolow transition on SDA while SCL remains high. This indicates that the start byte follows. This 8-bit start byte is made up of a 7-bit address plus an R/W bit indicator. All peripherals connected to the bus respond to the start condition and shift in the next eight bits (7-bit address + R/W bit). The bits arrive MSB first. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. An exception to this is the general call address, which is described in the General Call section. In the idle condition, the device monitors the SDA and SCL lines waiting for the start condition and the correct address byte. The R/W bit determines the direction of the data transfer. A Logic 0 LSB in the start byte means that the master writes information to the addressed peripheral. In this case, the AD7151 becomes a slave receiver. A Logic 1 LSB in the start byte means that the master reads information from the addressed peripheral. In this case, the AD7151 becomes a slave transmitter. In all instances, the AD7151 acts as a standard slave device on the serial bus. The start byte address for the AD7151 is 0x90 for a write and 0x91 for a read. In continuous conversion mode, the address pointers' autoincrementer should be used for reading a conversion result. This means that the two data bytes should be read using one multibyte read transaction rather than two separate single-byte transactions. The single-byte data read transaction may result in the data bytes from two different results being mixed. The user can also access any unique register (address) on a oneto-one basis without having to update all the registers. The address pointer register contents cannot be read. If an incorrect address pointer location is accessed or if the user allows the auto-incrementer to exceed the required register address, the following applies: * In read mode, the AD7151 continues to output various internal register contents until the master device issues a no acknowledge, start, or stop condition. The address pointers' auto-incrementer contents are reset to point to the status register at the 0x00 address when a stop condition is received at the end of a read operation. This allows the status register to be read (polled) continually without having to constantly write to the address pointer. In write mode, the data for the invalid address is not loaded into the AD7151 registers, but an acknowledge is issued by the AD7151.
*
WRITE OPERATION
When a write is selected, the byte following the start byte is always the register address pointer (subaddress) byte, which points to one of the internal registers on the AD7151. The address pointer byte is automatically loaded into the address pointer register and acknowledged by the AD7151. After the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master. A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If a stop condition is encountered by the AD7151, it returns to its idle condition and the address pointer is reset to 0x00. If a data byte is transmitted after the register address pointer byte, the AD7151 loads this byte into the register that is currently addressed by the address pointer register and sends an acknowledge, and the address pointer auto-incrementer automatically increments the address pointer register to the next internal register address. Thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses.
READ OPERATION
When a read is selected in the start byte, the register that is currently addressed by the address pointer is transmitted to the SDA line by the AD7151. This is then clocked out by the master device, and the AD7151 awaits an acknowledge from the master. If an acknowledge is received from the master, the address autoincrementer automatically increments the address pointer register and outputs the next addressed register content to the SDA line for transmission to the master. If no acknowledge is received, the AD7151 returns to the idle state and the address pointer is not incremented. The address pointers' auto-incrementer allows block data to be written to or read from the starting address and subsequent incremental addresses.
Rev. 0 | Page 21 of 28
AD7151
If a repeated start condition is encountered after the address pointer byte, all peripherals connected to the bus respond exactly as outlined previously for a start condition; that is, a repeated start condition is treated the same as a start condition. When a master device issues a stop condition, it relinquishes control of the bus, allowing another master device to take control of the bus. Therefore, a master wanting to retain control of the bus issues successive start conditions known as repeated start conditions.
GENERAL CALL
When a master issues a slave address consisting of seven 0s with the eighth bit (R/W bit) set to 0, this is known as the general call address. The general call address is for addressing every device connected to the serial bus. The AD7151 acknowledges this address and reads in the following data byte. If the second byte is 0x06, the AD7151 is reset, completely uploading all default values. The AD7151 does not respond to the serial bus commands (do not acknowledge) during the default values upload for approximately 2 ms. The AD7151 does not acknowledge any other general call commands.
AD7151 RESET
To reset the AD7151 without having to reset the entire serial bus, an explicit reset command is provided. This uses a particular address pointer word as a command word to reset the part and upload all default settings. The AD7151 does not respond to the serial bus commands (do not acknowledge) during the default values upload for approximately 2 ms. The reset command address word is 0xBF.
SDATA
START ADDR R/W ACK SUBADDRESS ACK
DATA
ACK
STOP
Figure 40. Bus Data Transfer
WRITE SEQUENCE
S
SLAVE ADDR A(S) LSB = 0
SUB ADDR
A(S)
DATA
A(S) LSB = 1
DATA
A(S) P
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE A(M) = NO ACKNOWLEDGE BY MASTER
Figure 41. Write and Read Sequences
Rev. 0 | Page 22 of 28
07086-030
READ SEQUENCE
07086-029
SCLOCK
S
1-7
8
9
1-7
8
9
1-7
8
9
P
S
SLAVE ADDR A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M) P
AD7151 HARDWARE DESIGN CONSIDERATIONS
OVERVIEW
The AD7151 is an interface to capacitive sensors. On the input side, the sensor (CX) can be connected directly between the AD7151 EXC and CIN pins. The way it is connected and the electrical parameters of the sensor connection, such as parasitic resistance or capacitance, can affect the system performance. Therefore, any circuit with additional components in the capacitive front end, such as overvoltage protection, has to be carefully designed considering the AD7151 specified limits and information provided in this section. On the output side, the AD7151 can work as a standalone device, using the power-up default register settings and flagging the result on digital outputs. Alternatively, the AD7151 can be interfaced to a microcontroller via the 2-wire serial interface, offering flexibility by overwriting the AD7151 register values from the host with a user-specific setup.
RGND1 DATA
PARASITIC RESISTANCE TO GROUND
CIN
CDC
CX
RGND2
Figure 43. Parasitic Resistance to Ground
The AD7151 CDC result is affected by a leakage current from CX to ground; therefore, CX should be isolated from the ground. The equivalent resistance between CX and ground should be maximized (see Figure 43). See Figure 8, Figure 9, Figure 10, and Figure 11.
PARASITIC CAPACITANCE TO GROUND
PARASITIC PARALLEL RESISTANCE
CGND1
CIN
CDC
DATA
CIN CDC DATA
CX
CX
RP
CGND2
07086-031
EXC
EXC
Figure 42. Parasitic Capacitance to Ground
Figure 44. Parasitic Parallel Resistance
The CDC architecture used in the AD7151 measures the capacitance CX connected between the EXC pin and the CIN pin. In theory, any capacitance CGND to ground should not affect the CDC result (see Figure 42). The practical implementation of the circuitry in the chip implies certain limits, and the result is gradually affected by capacitance to ground (see Table 1 for information about the allowed capacitance to GND for CIN and information about excitation). See Figure 4, Figure 5, Figure 6, and Figure 7.
The AD7151 CDC measures the charge transfer between the EXC and CIN pins. Any resistance connected in parallel to the measured capacitance CX (see Figure 44), such as the parasitic resistance of the sensor, also transfers charge. Therefore, the parallel resistor is seen as an additional capacitance in the output data. The equivalent parallel capacitance (or error caused by the parallel resistance) can be approximately calculated as
CP =
1 RP x f EXC x 4
where RP is the parallel resistance and fEXC is the excitation frequency. See Figure 13.
Rev. 0 | Page 23 of 28
07086-033
07086-032
EXC
AD7151
PARASITIC SERIAL RESISTANCE INPUT EMC PROTECTION
39k CX
CIN CDC DATA
82k 68pF 10k
CIN 22pF EXC
07086-036
RS1
CDC
47pF
CX
GND
Figure 47. AD7151 CIN EMC Protection
EXC
07086-034
RS2
Figure 45. Parasitic Serial Resistance
The AD7151 CDC result is affected by a resistance in series with the measured capacitance. The total serial resistance (RS1 + RS2 in Figure 45) should be on the order of hundreds of . See Figure 12.
Some applications may require an additional input filter for improving electromagnetic compatibility (EMC). Any input filter must be carefully designed, considering the balance between the system capacitance performance and system electromagnetic immunity. Figure 47 shows one of the possible input circuit configurations significantly improving the system immunity against high frequency noise and slightly affecting the AD7151 performance in terms of additional gain and offset error.
INPUT OVERVOLTAGE PROTECTION
CDC RS1 CX RS2 EXC CIN
POWER SUPPLY DECOUPLING AND FILTERING
1k 0.1F VDD SDA CDC
07086-035
VDD
10F 1k 1k
SCL
GND
Figure 46. AD7151 CIN Overvoltage Protection
The AD7151 capacitive input has an internal ESD protection. However, some applications may require an additional overvoltage protection, depending on the application-specific requirements. Any additional circuit in the capacitive front end must be carefully designed, especially with respect to the limits recommended for maximum capacitance to ground, maximum serial resistance, maximum leakage, and so on.
Figure 48. AD7151 VDD Decoupling and Filtering
The AD7151 has good dc and low frequency power supply rejection but may be sensitive to higher frequency ripple and noise, specifically around the excitation frequency and its harmonics. Figure 48 shows a possible circuit configuration for improving the system immunity against ripple and noise coupled to the AD7151 via the power supply. If the serial interface is connected to the other circuits in the system, it is better to connect the pull-up resistors on the other side of the VDD filter than connect to the AD7151. If the AD7151 is used in standalone mode and the serial interface is not used, it is better to connect the pull-up resistors directly to the AD7151 VDD.
Rev. 0 | Page 24 of 28
07086-058
GND
AD7151
APPLICATION EXAMPLES
0.1F 10k 10k
VDD
CIN
AD7151
SDA SCL 3V BATTERY
CSENS
EXC
OUT 1k LED
Figure 49. AD7151 Standalone Operation Application Diagram
3.3V 0.1F 1k 1k
VDD
AD7151
CIN CSENS EXC SDA SCL OUT SDA SCL IRQ
HOST MICROCONTROLLER
07086-037
GND
GND
Figure 50. AD7151 Interfaced to a Host Microcontroller
1k 0.1F VDD 39k CSENS 82k 68pF 10k CIN 22pF EXC 47pF 10F
3.3V 1F
ADP1720-3.3
1F
VSUPPLY
AD7151
SDA SCL
1k
1k
R1
OUT
Q1
07086-061
GND
Figure 51. AD7151 Standalone Operation with EMC Protection and Optional Serial Interface
Rev. 0 | Page 25 of 28
07086-038
OUT
AD7151 OUTLINE DIMENSIONS
3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8 0 0.80 0.60 0.40
10 6
1
5
5.15 4.90 4.65
SEATING PLANE
0.23 0.08
Figure 52. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7151BRMZ 1 AD7151BRMZ-REEL1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP]
Package Option RM-10 RM-10
Branding C5M C5M
Z = RoHS Compliant Part.
Rev. 0 | Page 26 of 28
AD7151 NOTES
Rev. 0 | Page 27 of 28
AD7151 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07086-0-11/07(0)
Rev. 0 | Page 28 of 28

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